/*************************************************************************
 *				SRLOS TEAM ALL RIGHT RESERVED
 *@filename		int.h
 *@autor		bloceanc
 *@date			08/07/2010
 *@note			interrupt control
 *************************************************************************/
#ifndef _INT_INTERRUPT_
#define _INT_INTERRUPT_

#include "io_mapping.h"		// for regirst address swap
/* Interrupt Vector Values */
// interrupt sources, emumeration values also be the offset values in OFFSET VALUE REGISTER
// WARNNING: DO NOT Change the order of enum elements.
typedef enum _int_source
{
	/* interrupt source */
	INT_EINT0 = 0,
	INT_EINT1,
	INT_EINT2,
	INT_EINT3,
	INT_EINT4_7,
	INT_EINT8_23,
	INT_CAM,
	INT_nBATT_FLT,
	INT_TICK,
	INT_WDT_AC97,
	INT_TIMER0,
	INT_TIMER1,
	INT_TIMER2,
	INT_TIMER3,
	INT_TIMER4,
	INT_UART2,
	INT_LCD,
	INT_DMA0,
	INT_DMA1,
	INT_DMA2,
	INT_DMA3,
	INT_SDI,
	INT_SPI0,
	INT_UART1,
	INT_NFCON,
	INT_USBD,
	INT_USBH,
	INT_IIC,
	INT_UART0,
	INT_SPI1,
	INT_RTC,
	INT_ADC = 31,

	/* interrupt sub source */
	INT_RXD0 = 32,	// INT_UART0     	0,
	INT_TXD0,     	// INT_UART0     	1,
	INT_ERR0,		// INT_UART0 		2,
	INT_RXD1,		// INT_UART1 		3,
	INT_TXD1,		// INT_UART1 		4,
	INT_ERR1,		// INT_UART1 		5,
	INT_RXD2,		// INT_UART2 		6,
	INT_TXD2,		// INT_UART2 		7,
	INT_ERR2,		// INT_UART2 		8,
	INT_TC,			// INT_ADC 			9,
	INT_ADC_S,		// INT_ADC 			10,
	INT_CAM_C,		// INT_CAM 			11,
	INT_CAM_P,		// INT_CAM 			12,
	INT_WDT,		// INT_WDT_AC97 	13,
	INT_AC97,		// INT_WDT_AC97 	14,
	INT_TYPE_ERROR, // a error interrupt type,an error maybe accured!
}int_source;

/* IRQ service handle definition */
typedef void (*irq_service)(void);

/* interrupt data structure */
typedef struct _int_data
{
	unsigned short type; // interrupt type
	unsigned char issubsrc; // indicate whether has sub interrupt sources, 1 has sub interrupt sourceses;otherwise havn't.
	unsigned char parent_type; // used for sub sources.
	unsigned int mask; // mask value for this interrupt type
	irq_service service; // service handler
}int_data;

/* interrupt registers */
#define	R_SRCPND		(*((unsigned int *)IO_PIO2VIO(0x4A000000)))
#define R_INTMASK		(*((unsigned int *)IO_PIO2VIO(0x4A000008)))
#define R_INTPND		(*((unsigned int *)IO_PIO2VIO(0x4A000010)))
#define R_INTOFFSET		(*((unsigned int *)IO_PIO2VIO(0x4A000014)))
#define R_SUBSRCPND		(*((unsigned int *)IO_PIO2VIO(0x4A000018)))
#define R_SUBINTMASK	(*((unsigned int *)IO_PIO2VIO(0x4A00001C)))

#endif /* _INT_INTERRUPT_  */
